Appeal 2007-1274
Application 10/850,897
1. Claims 7-13, 15[,] and 19-21 are rejected under 35
U.S.C. [§] 103(a) as being unpatentable over Rao et al. (US Pat.
6,808,986, hereinafter Rao) in view of Prall et al. (US Pat.
5,345,104, hereinafter Prall).
…
According to the Examiner (Answer 4):
Rao discloses in fig. 1 a memory device (col. 2, lines 13-
58), comprising: a silicon substrate 12 having a layer of tunnel
oxide 18 situated above a channel in the substrate 12; a floating
gate (see Abstract) having silicon nanocrystals 20 therein
disposed over the tunnel oxide layer 18; silicon nanocrystals 20
embedded in a control oxide layer 22; a polysilicon control gate
24 over the floating gate; and lateral nitride spacers 26
surrounding the floating gate stack.
Rao discloses a memory structures as describe[d] above
but fails to disclose the spacers is [sic] formed of oxide layer.
However, Prall teaches a similar memory structures having the
oxide layer 22 as a spacers [sic] (col. 4, lines 13-20 and fig. 2).
It would have been obvious to one of ordinary skill in the art at
the time the invention was made to modify the invention of Rao
by forming the oxide spacers as taught by Prall since the
material such as oxide/nitride layer is recognized equivalent
material for forming the spacers in a memory device.
The Appellants argue (Br. 10) that:
[E]ven if such a modification would be obvious to one of skill
in the art, it still would not result in Appellants' claimed
invention because the oxide spacers taught by Prall et al. are
significantly different from the thermal oxide spacers claimed
by Appellants….
The Examiner asserts that the claimed “thermal oxide” spacer is no different
from the prior art oxide spacer since the claimed “thermal oxide” spacer is
an oxide spacer made from an oxide layer produced by thermal oxidation
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