Appeal 2007-1647
Application 10/631,841
THE INVENTION
The disclosed invention relates generally to an interface circuit, and
more particularly, to a low jitter input buffer (Specification 1).
Independent claim 1 is illustrative:
1. An input buffer receiver comprising:
a buffer input portion for receiving an input signal, said
buffer input portion comprising a bias node;
a large capacitor coupled between the bias node and a
lower supply voltage for providing a coupling ratio between a
capacitance value of said large capacitor and a capacitance
value of a parasitic capacitor coupled between said bias
node and a ground reference point is approximately equal to
a unity value such that a biasing voltage at said biasing node
follows said lower supply voltage to minimize effects of a
ground noise signal between the lower supply voltage and
the ground reference point; and
a buffer output portion in communication with the buffer
input portion for producing an output signal.
THE REFERENCES
Applicant’s Admitted Prior Art (AAPA), see Fig. 1, labeled “FIG. 1 ─ Prior
Art,” see also pages 61-62, paragraphs 0014-0016.
Rapp US 6,373,328 B2 Apr. 16, 2002
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