Appeal 2007-2083
Application 10/035,584
STATEMENT OF CASE
Appellant appeals under 35 U.S.C. § 134 from a final rejection of
claims 1-37. We have jurisdiction under 35 U.S.C. § 6(b).
Appellant invented systems and methods for performing a floating
point remainder operations with embedded status information associated
with the floating point operand. (Specification [02]).
Representative independent claim 1 under appeal reads as follows:
1. A system for providing a floating point remainder, comprising:
an analyzer circuit configured to determine a first status of a
first floating point operand and a second status of a second floating
point operand based upon data within the first floating point operand
and data within the second floating point operand respectively; and
a results circuit coupled to the analyzer circuit and configured
to assert a resulting floating point operand containing the remainder of
the first floating point operand and the second floating point operand
and a resulting status embedded with the resulting floating point
operand.
The Examiner rejected claims 1-37 under 35 U.S.C. § 103(a).
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Huang US 5,995,991 Nov. 30, 1999
Nakano US 5,065,352 Nov. 12, 1991
Claims 1-37 were also provisionally rejected in the Final Rejection
under the judicially created doctrine of double patenting. The Answer does
not expressly withdraw the rejection, but neither does it repeat it. See Ex
2
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