Appeal 2007-2101
Application 10/859,552
comprising a gate insulation layer, a polysilicon layer and a cap layer to
form a gate electrode having a cap layer, (2) forming silicide regions
comprising a first metal in said drain and source regions, and (3) exposing
the top of the gate electrode (i.e., removing the cap layer), and forming a
nickel silicide/cobalt silicide layer stack region in said gate electrode (claim
18).
Claim 18 is illustrative:
18. A method of forming a field effect transistor, the method comprising:
forming a layer stack including at least a gate insulation layer, a polysilicon
layer and a cap layer above a silicon region formed on a substrate;
patterning said layer stack to form a gate electrode having a top surface
covered by at least said cap layer;
forming a drain and a source region adjacent to said gate electrode;
forming silicide regions comprising a first metal in said drain and source
regions;
exposing said top surface of said gate electrode; and
forming a nickel silicide/cobalt silicide layer stack region in said gate
electrode.
The Examiner relies on the following prior art references as evidence
of unpatentability:
Yu US 6,376,320 B1 Apr. 23, 2002
Maex US 2002/01581170 A1 Oct. 17, 2002
Wieczorek US 6,620,718 B1 Sep. 16, 2003
The rejection as presented by the Examiner is as follows:
1. Claims 18-22 are rejected under 35 U.S.C. § 103(a) as being
unpatentable over Maex in view of Yu or Wieczorek.
2
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