Appeal 2007-2127
Reexamination Control No. 90/006,621
is similar. Claim 24 recites "clock driven means for periodically activating
said interrupt input at brief predetermined time intervals so as to interrupt
the execution of an executing processing thread . . . upon each activation of
said interrupt input." Claim 26 recites "clock timer for periodically
activating said interrupt operation at brief predetermined time-sliced
intervals so as to interrupt the execution of an executing . . . thread . . . and
to take therefrom control of the central processor upon each activation of
said interrupt operation"; claim 75 is similar. Claim 69 recites "an interrupt
service routine for preemptively taking control of the microprocessor in
response to each activation of said interrupt input." Compare this to
claims 10, 14, and 17, which recite "means to repeatedly activate said
interrupt input so as to interrupt execution of said first thread"; i.e., they only
recite interrupting execution of a first thread (although they do not preclude
interrupting a plurality of threads). Therefore, most of the claims require
that an executing thread is interrupted upon each actuation of an interrupt—
if a thread cannot be interrupted, it would not meet the claim limitation.
The claims do not recite preempting more than one thread, but cover
preempting all threads. For example, claim 1 recites "preempting an
executing processing thread . . . in response to each actuation of said
interrupt operation," "passing control to another processing thread," and
"thereafter returning control of the central processing unit to a previously
preempted thread." Claim 1 does not expressly recite preempting the
"another processing thread" to return control, as in normal multithreading,
nevertheless, it does not exclude it and Patent Owner interprets the claims to
read on conventional multithreading where each thread is interrupted.
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