Appeal No. 95-3917
Application 07/861,144
circuit chip, since the method is detailed later in the claim. The step of "providing coded input signals . . .
in accordance with said target value and said fabricating process" is described, for example, as
progressively increasing the value of resistance until the optimum value of resistance is obtained as part of
the fabricating process (e.g., specification, page 7). Nor do we see a problem with the recitation that "each
conductive gate includes a corresponding passive element" since this clearly means that a gate, say G8 in
figure 1, has a corresponding passive element, R8 in figure 1; the limitation does not state that the gate is
a passive element.
For the reasons discussed above, the rejection of claims 1-22 is reversed.
35 U.S.C. § 102(b)
Figure 3J of Merrick discloses a digitally controlled resistance D . "The output of the counter 66
R
is digital and is applied through a decoder 69 so as to set the resistance of D at a desired value. The
R
internal circuit of the digitally controlled resistance D is schematically represented by series resistors r ,R 1
r and r that are respectively shunted by switches s , s and s ; but in actuality, the resistor connections2 3 1 2 3
would be much more complicated" (column 18, lines 54-61). "At each count, the coded output of the
counter 66 changes, and each output causes different combinations of the switches s , s and s in D to1 2 3 R
open or close, thereby placing the corresponding resistor combination in the attenuator circuit" (column 19,
lines 9-13). Thus, Merrick has a decoder and a network (D ) of a plurality of interconnected passive
R
elements (r , r , and r ) and a plurality of corresponding logic gates (s , s and s ).1 2 3 1 2 3
- 6 -
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Next
Last modified: November 3, 2007