Ex parte BOSWELL et al. - Page 9




          Appeal No. 95-4636                                                          
          Application 08/027,868                                                      

          that regard, we reject the appellants' argument:  "While it is              
          true that the Crowdis patent also teaches the similar                       
          function, the caller ID number is retrieved through the FPGA                
          circuitry in Applicants' data terminal."  The appellants have               
          not shown where in any rejected claim is the requirement that               
          the caller ID number is retrieved through the FPGA circuitry.               
               What Butler clearly does not disclose is the claimed                   
          field programmable gate array (FPGA) which receives a                       
          plurality of control signals, address signals, data signals,                
          and sensed signals from around the data terminal, and provides              
          a plurality of gated outputs.  Moreover, according to claim 6,              
          the UART must be connected to an 8-bit data bus which connects              
          to the plural gated output digital ports from the field                     
          programmable gate array.                                                    
               With regard to the "FPGA" feature of the invention, the                
          examiner states (answer at 5):                                              
               FPGAs are again well known in the art for allowing                     
               the user to program an integrated circuit to a                         
               specific need such as generation of complex logic                      
               functions as an alternative to more expensive                          
               applications specific integrated circuits.  The                        
               number and order of FPGAs, and the number of                           
               resident logic gates is apparently an obvious matter                   
               [of] design that will depend on the [a] system                         
               requirement.  Thus, it would have been obvious to                      
               one of ordinary skill in the art at the time the                       
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