Appeal No. 95-4636
Application 08/027,868
circuitry between the computer 10 and the UART 26 in Butler,
much less such a layer comprising an FPGA.
The examiner has resorted to speculation to account for
the necessary connection between the FPGA and the UART. The
examiner first proposes to change certain unspecified logic
gates of Butler to an FPGA, and then concludes that the
connection of the UART to the FPGA would follow (answer at
11). According to the examiner, an FPGA implementation of
Butler's data terminal would inevitably result in the
appellants' claimed invention, and the data bus of the UART
"must be" connected to the data ports of the FPGA (answer at
12). The conclusion is not supported by the evidence of
record and amounts to speculation. Again, it is noted that
Figures 4 and 5 of Butler do not illustrate how the various
detailed circuitry is connected to the UART identified in
Figure 1. The examiner may not, because he or she may doubt
the invention is patentable, resort to speculation, unfounded
assumptions or hindsight reconstruction to supply deficiencies
in the factual basis supporting the rejection. See In re
Warner, 379 F.2d 1011, 1017, 154 USPQ 173, 178 (CCPA 1967),
cert. denied, 389 U.S. 1057 (1968). The filling in of the
11
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