Appeal No. 95-4636
Application 08/027,868
invention was made to use an FPGA in place of a
cascade of separate logic gates for connecting the
CPU and memories used by Butler et al. as shown in
Figs. 4 and 5 for the purpose of using a standard,
off-the-shelf circuits for programming special
functions as desirable.
Figure 5 of Butler does show several logic circuits,
i.e., decoders 150 and 156 and data selector 138, each of
which indeed can be implemented by an FPGA circuit. However,
the examiner evidently has overlooked a difference between the
appellants' claimed invention and Butler.
In Butler, the overall system architecture is
particularly illustrated in its Figure 1. As shown, there is
no system component positioned between the computer 10 (CPU,
RAM and EPROM) and the UART 26. Thus, whatever circuitry the
examiner proposes to implement by FPGA instead of the
disclosed implementation in Butler is not disposed between the
computer 10 and the UART 26 as is required by the appellants'
claim 6. Butler's Figures 4 and 5 evidently do not show the
UART or how it is connected to the various circuit which are
shown. The examiner has articulated no reasonable motivation
for one with ordinary skill in the art to add another layer of
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