Appeal No. 93-1883
Application No. 07/759,691
4, 11 and 13 have been amended subsequent to the final
rejection.
The subject matter on appeal is directed to a method for
“fully” testing and burning-in integrated circuit chips before
they are incorporated into a high density interconnect circuit
or other hybrid circuit. This subject matter is adequately
illustrated in independent claims 11 and 13, which are
reproduced below:
11. A method for fully testing and burning-in integrated
circuit chips before incorporating said chips into a high
density interconnect circuit or other hybrid circuit, said
chips having a plurality of chip pads thereon, said method
comprising the steps of:
temporarily situating an integrated circuit chip on a
test substrate with said chip pads facing away from said
substrate, said test substrate having a plurality of pins
extending through an entire thickness of said substrate but
not in a region where said chip is situated, each of said chip
pads being integrally connected to a temporary buffer pad,
respectively, so as to provide an electrically conductive path
therebetween;
temporarily electrically connecting said chip pads with
predetermined ones of said pins at locations where said
predetermined pins emerge from said test substrate by
providing wires to electrically connect said predetermined
pins to said temporary buffer pads, each of said wires being
bonded at a first end to a respective one of said
predetermined pins and being bonded at a second end to a
respective one of said temporary buffer pads;
testing and burning-in said integrated circuit chip; and
2
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