Appeal No. 93-1883
Application No. 07/759,691
retrieving said integrated circuit chip from said test
substrate for subsequent incorporation into a high density
interconnect circuit or other hybrid circuit unless said chip
is not fully operative.
13. A method for fully testing and burning-in integrated
circuit chips before incorporating said chips into a high
density interconnect circuit or other hybrid circuit, said
chips having a plurality of chip pads thereon and being coated
with an insulative layer, each of said chip pads being
electrically
connected to a temporary buffer pad, respectively, through a
metal-filled via, respectively, said method comprising the
steps of:
temporarily situating an integrated circuit chip on a
test substrate with said chip pads facing away from said
substrate, said test substrate having a plurality of pins
extending through an entire thickness of said substrate but
not in a region where said chip is situated;
temporarily electrically connecting said chip pads with
predetermined ones of said pins at locations where said
predetermined pins emerge from said test substrate by
providing wires to electrically connect said predetermined
pins to said temporary buffer pads, each of said wires being
bonded at a first end to a respective one of said
predetermined pins and being bonded at a second end to a
respective one of said temporary buffer pads, each of said
temporary buffer pads, respectively, being offset relative to
each of said chip pads, respectively, connected thereto
through a respective metal-filled via;
testing and burning-in said integrated circuit chip: and
retrieving said integrated circuit chip from said test
substrate for subsequent incorporation into a high density
interconnect circuit or other hybrid circuit unless said chip
is not fully operative.
As evidence of obviousness, the examiner relies on the
3
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Next
Last modified: November 3, 2007