Appeal No. 95-1009
Application 07/858,632
method of fabricating semiconductor devices having grooves or
trenches in the surface of a substrate which are filled up
with a filling material by a bias ECR-CVD process and then
leveled (main brief, page 1).
Appellants state that the claims do not stand or fall
together (main brief, page 2) and present specific reasons for
the separate patentability of each claim on pages 2-5 of the
main brief. See 37 CFR § 1.192(c)(5)(1993). A copy of claims
1 through 6 taken from appellants’ brief is appended to this
decision.
The following references have been relied upon by the
examiner:
Kaanta et al. (Kaanta) 4,793,895 Dec. 27, 1988
Olmer 5,089,442 Feb. 18, 1992
Wolf, Silicon Processing for the VLSI Era, Volume 2:Process
Integration, pp. 237-239 and 285-286 (Lattice Press, 1990)
Claims 1 and 3 stand rejected under 35 U.S.C. § 102(b) as
anticipated by Wolf. Claims 1, 2, 4 and 5 stand rejected
under 35 U.S.C. § 102(b) as anticipated by the admitted prior
art. Claim 6 stands rejected under 35 U.S.C. § 102(b) as
2
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