Appeal No. 95-3889
Application 08/070,296
a multi-port RAM for storing data used during execution of
the operation instructions;
a sequence operation processor, coupled to said multi-port
RAM, for executing the operation instructions, said sequence
operation processor including a comparator for comparing a first
designated address of said multi-port RAM in a first operation
instruction with a second designated address of said multi-port
RAM in a second, subsequent operation instruction, and for
generating a comparison signal indicating a result of said
comparison, the second designated address of said multi-port RAM
being read in response to said generated comparison signal
indicating that said first and second designated addresses are not
equal to each other, wherein said sequence operation processor
simultaneously writes data to the first designated address of the
multi-port RAM and reads data from the second designated address
of the multi-port RAM when said generated comparison signal
indicates that said first and second designated addresses are not
equal to each other.
The references relied upon by the examiner as evidence of
obviousness are:
Loo 4,639,866 Jan. 27,
1987
Runaldue 5,062,081 Oct. 29,
1991
Appellant’s prior art admissions on pages 1-5 of the
specification.
Claims 1-3, 5 and 6 stand rejected under 35 U.S.C. § 102(b)
as anticipated by Loo.
2
Page: Previous 1 2 3 4 5 6 7 Next
Last modified: November 3, 2007