Appeal No. 95-4736
Application 08/084,801
a host interface 200 into the NOP controller 500 to initiate the process. The NOP controller 500
signals the decoder 550 with a NOP flag across line 503. In response to the flag, write enable
signals on line 553 which are generated by the decoder 550 are turned off. Thus, when an
instruction is decoded from the set of locations to be overridden, it will have no effect on any
stored data in the processor. The processor is disabled from changing data in response to
instructions in the particular set of memory locations in the microcode store 213 which stores the
program being replaced. While the NOP flag is produced, the pre-fetch mechanism 214 continues
to sequence through the instructions in the microcode store 213, and the set of instructions for the
new program is loaded into the microcode store at the appropriate location through the host
interface 200. Thus, the programs stored in the microcode store 213 which are not being replaced
continue to execute properly, without interruption, while the program being replaced is disabled
and a new program is substituted. After the operation is complete, the NOP controller 500 stops
asserting the NOP flag 503 so the new program is executed next time the pre-fetch mechanism
sequences through the set of locations.
Opinion
Appellants contend that the rejection of claims 1-39 is insufficient because the combination
of references does not describe specific limitations in the rejected claims, and the combination
taken as a whole does not otherwise suggest such limitations in the claimed subject matter. With
respect to independent claim 1, it is alleged that neither reference teaches disabling a processor
from changing data in response to instructions from a particular subset of instructions which are
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