Appeal No. 95-5032
Application 08/189,276
of claims 1-22, which constitute all the claims in the application.
The disclosed invention pertains to the area of a semiconductor memory apparatus. Such an
apparatus includes a plurality of memory cells, sense amplifiers, word lines and bit line pairs. The
invention has a hierarchical data organization in which corresponding bit line pairs are connected to
respective memory cells over a pair of sub-I/O lines. A particular feature of the invention is in the
manner in which control signals are applied to each sense amplifier in order to prevent erroneous
coupling of transient voltages from one bit line to another.
Representative claim 1 is reproduced as follows:
1. In a memory apparatus including a plurality of memory cells, word lines and bit line pairs,
said apparatus having a hierarchical data organization in which said plurality of memory cells are
arranged in rows and columns, and a plurality of sense amplifiers and corresponding bit line pairs
connected to respective memory cells receive data over a pair of sub-I/O lines corresponding to a
plurality of said bit line pairs, wherein all the memory cells connected to a selected word line are
selected and the pair of sub-I/O lines is connected to a corresponding bit line pair before activation of
the plurality of sense amplifiers, a method of transferring data over said sub-I/O lines to said plurality of
memory cells, comprising the steps of:
selecting a particular memory cell corresponding to a selected bit line pair;
receiving a plurality of distinct sense amplifier control signals, each sense amplifier control signal
being distinct for each sense amplifier associated with a common pair of sub-I/O lines;
connecting one bit line pair of said plurality of bit line pairs corresponding to said selected
memory cell to said sub-I/O lines; and
in response to the distinct sense amplifier control signals, activating the sense amplifier
connected to said selected bit line pair; whereby
2
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