Appeal No. 95-5032
Application 08/189,276
prior art. Figure 3 is described as an improvement on the memory of Figure 1 since it reduces the
parasitic capacitance of the bit line pairs due to the number of memory cells. The memory of Figure 3
achieves this reduction by dividing the single bit line pair into a plurality of bit line pairs and connecting
each of the divided bit line pairs to a single sub-input/output line pair through transfer gates. The
description of Figures 1-4 is followed by a section entitled “SUMMARY OF THE INVENTION.”
The summary of the invention states its object as “to solve the above described problems” (presumably
meaning the problems caused by the circuits shown in Figures 1 and 3). This section is followed by a
section entitled “BRIEF DESCRIPTION OF THE DRAWINGS.” The original specification describes
Figures 1 and 3 as follows:
Fig. 1 is a circuit diagram showing a structure of a conventional two-
port memory device;
Fig. 3 is a circuit diagram showing one example of a semiconductor
memory device which is not prior art but is considered to be the
background of the present invention; [specification, page 11].
The examiner has been relying on Figure 3 as prior art since a rejection was made in the
grandparent application to this application [S. N. 07/735,684]. The examiner has consistently
maintained his position since that time that Figures 1-4 were all considered to be admitted prior art.
Appellants began referring to Figures 3 and 4 as “prior art” after the examiner designated them as such.
Appellants referred to Figure 3 as prior art in papers filed July 29, 1992, June 24,
5
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 13 Next
Last modified: November 3, 2007