Appeal No.97-0582
Application 08/179,926
The invention relates to computer system architectures, and
more particularly to microprocessors that can execute multiple
instructions sets. Appellants disclose on pages 11 and 12 of the
specification that Figure 2 shows a simplified block diagram of a
CPU that can execute both reduced instruction set computer (RISC)
and complex instruction set computer (CISC) instructions. In
particular, Figure 2 shows that instructions are fetched and
supplied to a RISC instruction decoder (RISC ID 36) and a CISC
instruction decoder (CISC ID 36). Either the decoded RISC
instruction or the decoded CISC instruction is selected by MUX 46
and outputted to execute unit 48 for execution of the decoded
instruction.
The independent claim 1 is reproduced as follows:
1. A central processing unit (CPU)for processing
instructions from two separate instruction sets, said CPU
comprising:
first instruction decode means for decoding
instructions from a first instruction set, said first
instruction set having a first encoding of
instructions;
second instruction decode means for decoding only a
subset of instructions from a second instruction set,
said second instruction set having a second encoding of
instructions, said first encoding of instructions
independent from said second encoding of instructions;
select means, coupled to said first instruction decode
means and said second instruction decode means, for
selecting said decoded instruction from either said
2
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