Appeal No.97-0582
Application 08/179,926
Upon a closer review of Portanova, we fail to find that
Portanova suggests to those skilled in the art to provide an
additional CISC decoder. Portanova teaches in column 1, lines
15-23, that although the development of CISC software is simpler
and easier to use, the CISC hardware requires the use of very
large scale integration resulting in a highly complex
microprocessor hardware design. Portanova further teaches in
column 1, lines 24-42, that RISC systems require simpler
microprocessors, but require more functions to be done in
software. In column 3, lines 44-56, Portanova teaches that the
object of their invention is to provide a simple RISC
architecture which eases the hardwired decoding of instructions
which in turn speeds control paths but also can emulate CISC
instruction sets. Portanova teaches in column 4, lines 18-34,
that the Portanova RISC architecture responds to CISC
instructions by addressing a corresponding one of a plurality of
groups of RISC instructions, each corresponding to one of the
complex instructions. Thus, Portanova teaches that the same RISC
architecture may be use to process a CISC instruction so that the
simpler and faster RISC hardware may be used for both
instructions sets. From this teaching, Portanova leads those
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