Appeal No.97-0582
Application 08/179,926
first instruction decode means or from said second
instruction decode means; and
execute means for executing decoded instructions
selected by said select means, whereby instructions
from both said first instruction set and said second
instruction set are executed by said CPU.
The Examiner relies on the following references:
Onishi 3,764,988 Oct. 09, 1973
Bullions, III et al. (Bullions) 2 4,456,954 Jun. 26, 1984
Portanova et al. (Portanova) 4,992,934 Feb. 12, 1991
Claims 1 through 5, 14 through 16 and 18 through 20 stand
rejected under 35 U.S.C. § 103 as being unpatentable over
Portanova and Onishi. Claims 6 through 13 and 17 stand rejected
under 35 U.S.C. § 103 as being unpatentable over Portanova,
Onishi and Bullions.
Rather than reiterate the arguments of Appellants and the
3 4
Examiner, reference is made to the briefs and answers for the
2In the answer as well as the supplemental answer, the
Examiner invites us to consider an IBM technical disclosure as
well as Iwata, U.S. Pat. No. 4,691,278. However, the Examiner
has not rejected the claims based upon these references.
Therefore, we find that these references are not properly before
us for our consideration.
3Appellants filed an appeal brief on August 29, 1995. We
will refer to this appeal brief as simply the brief. Appellants
filed a reply appeal brief on November 29, 1995. We will refer
to this reply appeal brief as the reply brief. The Examiner
responded to the reply brief with a supplemental answer stating
that the reply brief has been entered. Appellants filed a
supplement to the brief on June 25, 1997. The Examiner responded
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