Appeal No. 97-2053
Application 08/229,624
(3) constructing bounding boxes around
the interconnect nets for the cell
placement; and
(4) computing the cost factor for the
cell placement as a first
predetermined function of the bounding
box overlap;
[see reply brief, pages 4-6].
The examiner responds that the claims do not require
placing cells on the integrated circuit [supplemental answer,
page 1]. The examiner notes that “[t]he claims require
computing overlap of said bounding boxes and the cost factor
as a function of the overlap (see claims 1, 15 and 17), but
not cost factor for the placement of cells on an integrated
circuit (IC) chip as cited” [ Id., page 3]. Finally, the
examiner reinforces this position by stating that “[t]he
rejected claims 1, 15 and 17 do not require locating cells on
a surface of an IC chip” [Id.].
In our view, the examiner has not properly considered
all of the claim recitations. Although we can agree that
Noble does broadly construct bounding boxes around
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