Appeal No. 97-2053
Application 08/229,624
interconnect nets, and Noble does broadly compute an overlap
of these bounding boxes, we cannot agree that Noble suggests
the computation of the cost factor as set forth in the claims
on appeal. Any cost factor in Noble is related to the best
location of a field of view for accessing a specific portion
of an integrated circuit. Noble has absolutely nothing to do
with determining the placement of cells on an integrated
circuit chip. Noble deals with an integrated circuit which
has already been designed and manufactured.
Claims 1 and 17 recite the function of “computing said
cost factor as a first predetermined function of said
overlap.” The phrase “said cost factor” refers to a cost
factor defined in the preamble of each of these claims.
Specifically, each of claims 1 and 17 defines the cost factor
in terms of “a placement of cells” on an IC chip or on a
surface. Therefore, the computation of this cost factor must
also be related to such cell placement. As noted above, Noble
has nothing to do with computing cost factors which relate to
such cell placement. Thus, the artisan would not have found
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