Ex parte SAKUMA et al. - Page 2




          Appeal No. 97-4425                                                          
          Application 08/619,418                                                      

          Kohno et al. (Kohno)     Patent No. 5,072,425     Dec. 10, 1991             
                                 Rejection on Appeal                                  
               Claims 11-16, 18 and 19 stand rejected under 35 U.S.C.                 
          § 102(b) as being anticipated by Kohno.  Claim 17 has been                  
          objected to as being dependent from a rejected claim.                       
                                    The Invention                                     
               The invention is directed to sense amplifier drive circuits            
          in a semiconductor memory.  The sense line and a conductor                  
          element are connected to both a first node of a first sense                 
          amplifier and the second node of a second sense amplifier.   Both           
          the sense line and the conductor element are for transferring               
          control signals to the sense amplifiers.  Representative                    
          independent claims 11 and 19 are reproduced below.                          
               11. A semiconductor memory device having a semiconductor               
          substrate having a major surface thereof, comprising:                       
               a first pair of bit lines, formed over the major surface,              
          having first and second bit lines, said first pair of bit lines             
          being coupled to a first memory cell, said first memory cell                
          causing a first potential difference between said first and                 
          second bit lines;                                                           
               a second pair of bit lines, formed over the major surface,             
          having third and fourth bit lines, said second pair of bit lines            
          being coupled to a second memory cell, said second memory cell              
          causing a second potential difference between said third and                
          fourth bit lines;                                                           
               a first sense amplifier having a first node, said first                
          sense amplifier being connected to the first pair of bit lines,             
          for amplifying the first potential difference between said first            

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