Appeal No. 97-4425
Application 08/619,418
and second bit lines in response to a first sense amplifier
control signal during a sensing operation;
a second sense amplifier having a second node, said second
sense amplifier being connected to the second pair of bit lines,
for amplifying the second potential difference between said third
and fourth bit lines in response to the first sense amplifier
control signal during the sensing operation;
a first sense line connected to said first and second nodes
for transferring the first sense amplifier control signal to said
first and second sense amplifiers, said first sense line being
formed over the major surface; and
a first conductive element connected to said first and
second nodes and formed in the major surface, for transferring
the first sense amplifier control signal to both said first and
second sense amplifiers during the sensing operation.
19. A semiconductor memory device having a semiconductor
substrate having a major surface thereof, comprising:
a first pair of bit lines;
a second pair of bit lines;
a first sense amplifier having a first node, said first
sense amplifier being connected to the first pair of bit lines,
for amplifying a potential difference between said first pair of
bit lines in response to a sense amplifier control signal during
a sensing operation;
a second sense amplifier having a second node, said second
sense amplifier being connected to the second pair of bit lines,
for amplifying a potential difference between said second pair of
bit lines in response to the sense amplifier control signal
during the sensing operation;
a sense line connected to said first and second nodes for
transferring the sense amplifier control signal to said first and
second sense amplifiers, said sense line being formed over the
major surface; and
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