Appeal No. 96-1319
Application 07/934,982
external leads connected to external circuitry such as shown in Figure 3 of Witt. We agree
with the examiner that the STAT 320 lead of Witt would have suggested the obviousness of
an interrupt generate lead as broadly recited in claim 4. With respect to claim 5, we must
determine the obviousness of maintaining information currently on an external lead within a
predetermined memory location of the processor. We find this feature to be obvious as
broadly recited in claim 5. The artisan would have appreciated and recognized the
obviousness of maintaining status flag registers which indicate the current status of various
ones of the external leads. Therefore, we sustain the rejection of claims 4 and 5.
Claims 6 and 7 recite a smart memory having either an external lead or a memory
location “for resetting said processor.” As noted above, the smart memory resulting from
the collective teachings of Nicoud, Witt and Nusinov would have a plurality of external leads
connected to external circuitry such as shown in Figure 3 of Witt. We agree with the
examiner that the RST 315 lead of Witt would have suggested the obviousness of a reset
lead as broadly recited in claim 6. With respect to claim 7, we again note that the artisan
would have appreciated and recognized the obviousness of maintaining status flag
registers which indicate the current status of various ones of the external leads. Therefore,
we sustain the rejection of claims 6 and 7.
Claim 8 recites a smart memory having a memory location “for causing said
processor to start and stop executing instructions.” Although the smart memory resulting
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