Appeal No. 96-1444
Application 08/130,577
and it is this teaching that is relied on in the rejection.
Our decision states (D8): "Although Wakeland is directed to
providing one of the background or foreground images to the
same display, one skilled in the art was taught by Tatsumi
that a memory can be used to hold separate images for separate
displays. One of ordinary skill in the art would have been
motivated to store separate images in Tatsumi in interleaved
byte planes in view of Wakeland or, alternatively, to output
the separate images in Wakeland to separate displays in view
of Tatsumi." This reasoning has not been contested.
Appellants argue that "[a] close examination of the
memory storage arrangement of Wakeland shows that two
different images are stored in disjoint sections of memory in
the video DRAM rather than in interleaved fashion" (RR4),
pointing to the address space in Table II. Table II shows the
CPU address space for data stored in the system DRAM 12
(col. 6, lines 12-15), not the video memory address space; the
DRAM 40 video memory organization and address space is shown
in Table III. Wakeland expressly states that "[t]he overlay
mode steered data is interleaved (i.e., background PEL data,
foreground PEL data, background PEL data, foreground PEL data,
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