Appeal No. 96-1444 Application 08/130,577 teaching of Wakeland fails to meet the interleaved memory limitation of claim 1. Appellants argue (RR5-6) that we have misinterpreted Wakeland's statement that "the VGA controller 32 disclosed herein, by use of the aforementioned 32-bit virtual data bus, is configured to interleave two independent images, a 256 color background and a 16 color foreground, seen by the CPU 4 as two discrete maps, or data sets, into the VGA DRAM 40 utilizing three of the four bit planes provided therein" (col. 3, line 67 to col. 4, line 5). Appellants argue (RR6): That interleaving refers to the bus arrangement in which the first two bytes from the background are followed by one byte from the foreground and one unused byte as shown in Table 3. However, the data are not stored in alternating byte planes in the video memory. We disagree. The "interleaving" at columns 3 to 4 is interleaving into the VGA DRAM 40, which is consistent with Table III showing an interleaved memory. That the bus may also interleave is not important. Appellants argue that "[i]f Wakeland were combined with Tatsumi et al., the result will only be the ability to produce overlays on the three displays A, B and C of Tatsumi et al." (RR6). This does not address the obviousness reasoning. Our - 8 -Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 NextLast modified: November 3, 2007