Appeal No. 96-1444
Application 08/130,577
etc.) in the VGA DRAM 40 in the following configuration [of
Table III]" (emphasis added) (col. 5, lines 65-68). A 32-bit
word D(0-31) read from the VGA DRAM 40 is one line from
Table III and contains two PELs from the background data set
on bits D(0-15) (first and second columns, which are
considered to be planes 0 and 1) and two PELs from the
foreground data set on bits D(16-23) (third column, plane 2).
Thus, the foreground and background images are "stored in said
memory in interleaved odd and even byte planes," as recited in
claim 1. Appellants' argument that the images are not
interleaved in memory is not persuasive.
It is noted that claim 1 recites that each frame of the
first and second video image "is stored in said memory in
interleaved odd and even byte planes." We noted in our
decision that "claim 1 does not recite how the first and
second images are distributed among the 'interleaved odd and
even byte planes'; each image could be distributed over all
byte planes" (D4-5). Table III of Wakeland shows a memory
comprising interleaved odd and even byte planes and two images
distributed in that memory. Appellants do not show how this
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