Appeal No. 1996-1767 Page 14
Application No. 08/220,410
The multiplication result from the multiplier M1 is
supplied to inter alia a first input terminal of an adder A1.
The multiplication result from the multiplier M2 is supplied
to inter alia a second input terminal of an adder-subtracter
AS1. Id. at ll. 38-42.
Because Fujii’s adder A1 sums the outputs of inter alia
the multiplier M1, which operates in synchronism with the
clock signal CK1, the adder output data in synchronism with
the clock signal CK1. This is the same clock signal with
which the flip-flop FF1 stores and outputs data. The clock
signal determines the frequency at which data are input and
output. Therefore, we find that the reference teaches
inputting and outputting signals at the same frequency.
Regarding claims 1-8, 12-13, and 25-31, the appellants
argue, “Fujii does not disclose ... the lattice wave digital
filter ....” (Appeal Br. at 8.) The examiner replies,
“relative to claim 1 this is merely ‘intended use’ and
relative to claim 25 it is only recited in the preamble with
the body of the claim defining the lattice wave digital filter
Page: Previous 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Next
Last modified: November 3, 2007