Appeal No. 1996-1767 Page 9
Application No. 08/220,410
samples of the first and second data streams at intervals T.
It also includes first and second subfilters clocked at the
frequency of 1/T and responsive to the outputs of the first
and second selectors respectively. Id. at ll. 31-41.
The reference’s first and second subfilters comprise a
common register-adder network including a series of N
registers and a series of N adders. The registers, which are
arranged in stages, are each clocked at the frequency of 1/T
to introduce a delay time T. The adders, which are also
arranged in stages, are each associated with respective
registers and sum the outputs of the associated registers and
the outputs of multipliers. The adders of the first to
(N-1)th stages supply the results of the summation to the
registers of the second to Nth stages. The output of the
adder of the Nth stage is supplied to a
demultiplexer. Id. at ll. 47-63. Figure 2 labels the adder
of the Nth stage as element 145.
Because Hirosaki’s adders sum the outputs of inter alia
the registers, which are clocked at the frequency of 1/T, the
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