Ex parte LIU - Page 2




          Appeal No. 1996-1767                                       Page 2           
          Application No. 08/220,410                                                  


          February 21, 1995, which was denied entry.  We affirm-in-part               
          and enter a new ground of rejection under 37 CFR § 1.196(b).                


                                     BACKGROUND                                       
               The invention at issue in this appeal relates to digital               
          filters.  It is an interleaved/retimed (IR) architecture for a              
          lattice wave digital filter (LWDF).  Prior architectures                    
          confront a designer with a trade-off between the amount of                  
          hardware needed to implement an LWDF and the variety of                     
          transfer functions that can be implemented thereby.  The IR                 
          architecture reduces the amount of hardware needed without                  
          sacrificing variety.                                                        


               Claim 1, which is representative for our purposes,                     
          follows:                                                                    
                    1.   An interleaved all-pass section for a                        
               lattice wave digital filter, comprising:                               
                    input means for inputting two interleaved                         
               signals, said two interleaved signals being input at                   
               a predetermined sampling frequency;                                    
                    a first adder/multiplier network (AMN) connected                  
               to said input means to receive said two interleaved                    
               signals;                                                               
                    a second adder/multiplier network (AMN) to                        
               output two output signals, said two output signals                     








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