Appeal No. 96-2160
Application 07/862,888
DECISION ON APPEAL
This is a decision on the appeal under 35 U.S.C. § 134 from the examiner’s
rejection of claims 1-8, which constitute all the claims remaining in the application.
An amendment after final rejection was filed on February 27, 1995 and was entered
by the examiner.
The disclosed invention pertains to a method and apparatus for optimizing the
dispatch latency of tasks in a data processing system. More particularly, a normal and
expedited scheduling path are provided for scheduling tasks to be run on the processor.
The normal or expedited scheduling path is selected based on the relationship between
the task currently being executed and a task selected for execution.
Representative claim 1 is reproduced as follows:
1. A method of enhancing task scheduling efficiency in a data processing system
having a processor, a memory, and a multitasking operating system for managing the
processor and the memory, the method comprising the data processing system
implemented steps of:
providing both a first expedited task scheduling path for tasks and a second task
scheduling path for tasks in a scheduler within said multitasking operating system;
assigning an execution priority to each of a plurality of tasks within said data
processing system for execution on the processor;
periodically placing selected tasks in a ready-to-run queue within said data
processing system;
2
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