Ex parte WAKEFIELD et al. - Page 2




          Appeal No. 96-2243                                                          
          Application 08/327,447                                                      



                    This is a decision on appeal from the final                       
          rejection of claims 19 through 27 and 30 through 39, all of                 
          the claims pending in the present application.                              
                    The invention relates to a package for semiconductor              
          chips.  In particular, referring to Figures 1 and 2, a semi-                
          conductor chip package 2 is shown with four chips 4.  A thin                
          printed circuit 8 (a first level interconnect), contains                    
          conductive tracks 20, and overlies the chips 4.  Each end 10                
          of the printed circuit 8 contains outer leads 12 which extend               
          outside the chip package 2.  Bond wires 38 (a second level                  
          interconnect), connect each chip to the tracks 20 on the upper              
          side of printed circuit 8.                                                  
                    Representative independent claims 19 and 30 are                   
          reproduced as follows:                                                      
                    19.  A semiconductor device comprising:                           
                    at least one semiconductor chip, the or each                      
          semiconductor chip having a plurality of chip bonding pads,                 
                    a first level interconnect comprising a printed                   
          circuit which overlies the at least one semiconductor chip and              
          is disposed adjacent to the chip bonding pads of the at least               
          one semiconductor chip, the printed circuit having contacts                 
          which are located on a side of the printed circuit remote from              
          the or each semiconductor chip and which overlie the at least               
          one semiconductor chip, and                                                 
                                          2                                           





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