Appeal No. 96-2243
Application 08/327,447
a second level interconnect comprising means for
electrically connecting the chip bonding pads to selected
contacts on the printed circuit,
the first interconnect being between the second
level interconnect and the or each semiconductor chip.
30. A semiconductor device comprising at least one
semiconductor chip, a package which encloses the at least one
semiconductor chip and a printed circuit which overlies and is
electrically connected to the at least one semiconductor chip
in the package and extends externally of the package to
provide a plurality of outer leads.
The Examiner relies on the following references:
Fukuta et al. (Fukuta) 4,751,482 June 14, 1988
Kishida 4,941,033 July 10, 1990
(filed Mar. 24, 1989)
Carlson et al. (Carlson) 4,953,005 Aug. 28,
1990
(filed Apr. 15, 1988)
Claims 19 through 27 stand rejected under 35 U.S.C.2
§ 103 as being unpatentable over Kishida in view of Fukuta.
Claims 30 through 32 stand rejected under 35 U.S.C.
2Claims 25 through 27 are not specifically mentioned by the Examiner
in the Office Action and Answer, however Appellants have assumed that the Examiner intended to include claims 25
through 27 in the 35 U.S.C. § 103 rejection over Kishida in view of Fukuta, thus we will treat them likewise.
3
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