Appeal No. 96-2243
Application 08/327,447
printed circuit which is remote from the
semiconductor chip or chips.
The Examiner responds that “Kishida is deemed to
teach a first level interconnect 41 formed between chip 2 and
a second level interconnect formed in printed circuit 4.”
(Answer at page 6).
The Examiner has repeatedly relied on Figure 7 of
Kishida, and we will assume the above comments are likewise
directed to this Figure. Noting that element 41 is not
labeled in Figure 7, we have located element 41 in Figure 1A
as being on the lower surface of wiring film 4 (i.e. printed
circuit 4). Column 2, lines 48 and 49, designate 41 as a
terminal. We are reluctant to deem 41 as an interconnect as
claimed by Appellants. However, if 41 is seen as the first
level interconnect as proposed by the Examiner, the Examiner
would then have us read the second level interconnect as
“formed in printed circuit 4.” Again, absent sufficient
labeling in Figure 7, we understand this to mean the
equivalent to wiring 43 in Figure 1A. Granting these
designations by the Examiner, we fail to see how the “second
level interconnect compris[es] means for electrically
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