Appeal No. 96-2499
Application No. 08/204,521
The invention pertains to efficient processing
performance within a superscalar microprocessor. More
particularly, a method and apparatus are provided for allowing
flag register renaming within a register alias table [RAT] and
for proper updating of the flag bits upon retirement of
operations that update flag bits.
Representative independent claim 16 is reproduced as
follows:
16. A microprocessor comprising:
a bus interface unit for interfacing with an internal
communication bus;
instruction decode and fetch unit coupled to said bus
interface unit for decoding and supplying a current set of
instructions within a common clock cycle wherein instructions
of said current set of instructions read flag registers, said
current set of instructions including a given instruction and
a previous instruction wherein said previous instruction
occurs previous to said given instruction in program code
order;
an execution unit for executing instructions;
an architecturally visible register file comprising
registers; and
register alias logic for renaming flag registers
associated with said current set of instructions processed
within said common clock cycle, said register alias logic
comprising:
2
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Last modified: November 3, 2007