Appeal No. 96-2499
Application No. 08/204,521
(a) a memory array for providing a plurality of
addressable entries for renaming said flag registers;
(b) array read logic coupled to said memory array
and coupled to said logic for supplying, said instruction
decode and fetch unit for addressing said memory array by said
flag registers and for supplying pointers to a set of physical
registers assigned to said flag registers;
(c) dependency logic for determining if said given
instruction of said current set of instructions reads a flag
register that is output by said previous instruction of said
current set of instructions; and
(d) comparison logic responsive to said dependency
logic for determining if flags of said flag register read by
said given instruction are a superset of flags of said flag
register output by said previous instruction of said current
set of instructions.
The examiner relies on the following reference:
Cocke et al. (Cocke) 4,992,938 Feb. 12,
1991
Claims 1 through 3, 5 through 40 and 42 through 50 stand
rejected under 35 U.S.C. § 103 as unpatentable over Cocke.
Reference is made to the brief and answer for the
respective positions of appellants and the examiner.
OPINION
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