Appeal No. 96-2820
Application 08/227,705
This is a decision on appeal from the final rejection of
claims 81 through 90, all of the claims pending in the present
application. Claims 1 through 80 have been canceled.
The invention relates to a processor having a
plurality of processing elements. In particular, Appellants
disclose on page 17 et seq. of the specification and
illustrate in Figure 4
a processing element 20(n). Each processor element 20(n) has
an input register 11 of M rows, a first memory bank 12 of J
rows (wherein J does not equal M), a first sense amplifier 40,
an ALU 13, an output register 16 of L rows, a second memory
bank 15 of
J rows and a second sense amplifier 42. The first sense
amplifier 40 is shared between the input register 11 and the
first memory bank 12. The second sense amplifier 42 is shared
between the output register 16 and second memory bank 15.
Representative independent claim 81 is reproduced as
follows:
81. Storage circuitry comprising:
2
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