Appeal No. 96-2820
Application 08/227,705
a first memory having a plurality of M rows of first
memory cells, each of said first memory cells connected to a
first pair of bit lines;
a set of M first word lines, each first word line
connected to a corresponding one of said first memory cells;
a second memory having a plurality of J rows of
second memory cells, where J does not equal M, each of said
second memory cells connected to a second pair of bit lines;
a set of J second word lines, each second word line
connected to a corresponding one of said second memory cells;
and
sense amplifier circuitry located between said first
memory and said second memory and connected to said first pair
of bit lines and said second pair of bit lines, said sense
amplifier circuitry including
a sense amplifier having a pair of sense
amplifier bit lines and a pair of output lines, said sense
amplifier producing an output signal on said
pair of output lines corresponding to a ratio of voltages on
said pair of sense amplifier bit lines,
a first gate circuit selectively connecting said
first pair of bit lines to said pair of sense
amplifier bit lines or isolating said first pair of bit
lines from said pair of sense amplifier bit lines, and
a second gate circuit selectively connecting
said second pair of bit lines to said pair of sense
amplifier bit lines or isolating said second pair of
bit lines from said pair of sense amplifier bit
lines,
whereby said sense amplifier circuitry produces said output
signal a) corresponding to data stored in a first memory cell
accessed by one of said first word lines when said first gate
circuit connects said pair of bit lines to said pair of sense
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Last modified: November 3, 2007