Appeal No. 96-2940
Application 08/259,073
This is a decision on appeal under 35 U.S.C. § 134 from
the final rejection of claims 1-25.
We reverse.
BACKGROUND
The disclosed invention is directed to a process for
forming very narrow closely spaced buried bit lines.
Claim 18 is reproduced below.
18. A method of forming a plurality of self-aligned
closely spaced very narrow buried conductive lines in a
semiconductor substrate, comprising the steps of:
providing a thin insulating layer on the surface of
the semiconductor substrate,
forming masking stripes having vertical sidewalls
over the thin insulating layer,
forming polysilicon spacers on the vertical
sidewalls of the masking stripes,
forming a glass layer between the spacers,
preferentially etching the polysilicon spacers
forming narrow openings between the masking lines and the
glass layer, and
implanting impurity ions into said substrate through
the narrow openings to form conductive buried lines.
The Examiner relies upon the following prior art:
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