Appeal No. 96-3085
Application 08/274,655
processor execution cycles [brief, page 6].
The examiner responds that Peet discloses a counter that
counts machine cycles in the synchronization process of the
CPU's, said counter is stopped when it reaches a maximum
value, which indicates that the CPU's are in synchronization
[answer, page 5]. The Examiner cites column 9, line 65 to
column 10, line 17 of Peet which state that: " A cycle counter
71 is coupled to the clock 17 ... to count machine cycles
which are Run cycles (but not Stall cycles). This counter 71
includes a count register having a maximum count value
selected to represent the period during which the maximum
allowable drift between CPU's would occur ...; when this count
register overflows [, an]action is initiated to stall the
faster processors [until slower
processor or processors catch up]. This counter 71 is reset
whenever synchronization is done ... circuit 65." The
Examiner concludes that the counter of Peet does stop
counting, and the step[s] of counting processor execution
cycles associated with a specific task, and [of] generating a
5
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