Appeal No. 96-3085
Application 08/274,655
68]. The objective is to run these three CPU's in
synchronization to
assure redundancy. Whenever they are out of synchronization
in a machine cycle, the counter register 71, which is
preloaded with a maximum allowable drift count value, is
decremented by one. When the counter reaches the maximum
allowable drift value, the processing in the faster CPU or
CPU's is stalled, synchronization among the CPU's is obtained,
and the counter is reset. Thus, there is an interrupt signal
when the counter reaches a predetermined value.
However, the counting done by the counter of the
invention is different from that done by counter 71 of Peet.
Peet's counter counts all the machine cycles continuously as
the CPU's are processing incoming instructions, which might
include interrupts, whereas the Appellant's counter counts
only those machine cycles which are exclusively ascribed to a
specific task, out of the many other multiple tasks, and all
the multiple tasks are being executed by a single CPU. Thus,
if an interrupt occurs due to the need to service another
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