Appeal No. 96-3234
Application 08/184,446
and second memory so that the m-bit data is stored in the
first memory and the n-bit pointer is stored in the second
memory.
Independent claim 1 is reproduced as follows:
1. An error correcting memory system which writes
and reads m-bit data and an error marking n-bit pointer by a
predetermined rule, comprising:
a first memory for recording said m-bit data;
a second memory for recording said n-bit pointer;
an address generating unit for generating the ad-
dress signals of said first and second memories by a predeter-
mined rule; and
a writing/reading control signal generating unit for
generating the respective writing and reading control signals
of said first and second memories by receiving the writing and
reading control signals and responding to a data/pointer
differentiating signal,
wherein m and n are integers greater than or equal
to one.
The Examiner relies on the following reference:
Ozaki et al. (Ozaki) 4,719,628 Jan. 12, 1988
Claims 1 through 13 stand rejected under 35 U.S.C.
§ 112, first paragraph, as being based upon a nonenabling
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