Appeal No. 96-3234
Application 08/184,446
in the second memory as claimed in Appellant's claim 1.
Furthermore, neither reference teaches or suggests a data bus
driving unit for driving an m + n bit data bus operatively
connected to a memory whose capacity is m + n bits bi-
directionally by dividing said m + n bit data into m-bits and
n-bits in response to a data input control signal and a
pointer writing control signal as recited in Appellant's
independent claim 3. Therefore, we will not sustain the
Examiner's rejection of claims 1 through 4 and 7 through 12
under 35 U.S.C. § 103 as being obvious over Ozaki.
Therefore, we have not sustained the rejection of
claims 1 through 13 under 35 U.S.C. § 112, first paragraph, or
the rejection of claims 1 through 4 and 7 through 12 under 35
U.S.C. § 103. Accordingly, the Examiner's decision is
reversed.
REVERSED
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