Appeal No. 96-3234
Application 08/184,446
Examiner's position is set forth in Paper No. 4. Turning to
Paper No. 4,
the Examiner states that the admitted prior art in Appellant's
specification on pages 1 through 3 shows that there are 8 bit
data and a one bit pointer. The Examiner argues that the
memory is arranged to store by byte so that the pointer is
stored in a byte location thereby wasting the other 7 bits.
The Examiner argues that Ozaki discloses a system where the
pointer memory is equal to the number of bits of the pointer.
Appellant argues on page 23 of the appeal brief that
the admitted prior art and Ozaki fail to teach a
writing/reading control signal generating unit for generating
the respective writing and reading control signals of first
and second memories by receiving the writing and reading
control signals and responding to a data point differentiating
signal as recited in claim 1. On page 27 of the appeal brief,
Appellant argues that the admitted prior art and Ozaki fail to
teach or suggest a data bus driving unit for driving an m + n
bit data bus operatively connected to said memory bi-
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