Appeal No. 96-3236
Application 08/295,493
application.
The invention pertains to an error detection scheme for a multiple processor system which uses
compressed signature collection and voting techniques to ensure process integrity.
Representative independent claim 1 is reproduced as follows:
1. A multiprocessor computer system with error detection capability for processing multiple
instruction sets, each instruction set of said multiple instruction sets comprising a plurality of instructions,
said multiprocessor computer system comprising:
a plurality of processors, each processor independently and asynchronously processing at least
some of said multiple instruction sets from the other of said plurality of processors;
a plurality of hardware signature generation means, each hardware signature generation means
being associated with a respective processor of said plurality of processors for generating a
compressed hardware signature contemporaneous with and substantially uniquely corresponding to said
respective processor's processing of a selected instruction set of said multiple instruction sets;
selection means for identifying said selected instruction set for comparison of respective
compressed hardware signatures from at least two hardware signature generation means of said
plurality of hardware signature generation means; and
voting means coupled to receive each of said respective compressed hardware signatures for
comparing said signatures for an error condition, an error condition being identified if a predefined
comparison failure is detected between the received compressed hardware signatures.
The examiner relies on the following references:
Danielsen et al. (Danielsen) 5,136,704 Aug. 4, 1992
2
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