Appeal No. 96-3274
Application 08/173,408
said micro-engine" to correspond to the "adapter interface
host address space [101]" in figures 3 and 4, described at
column 10, lines 37-45, and column 24, line 14 (EA3). The
Examiner finds the "network interface module" to correspond to
the "network interface logic 104" mentioned at column 10,
line 3 (EA3). The flow diagram for these elements is shown in
figure 3 of Petersen.
We see several problems with the rejection. First, the
Examiner does not identify what element in Petersen
corresponds to the "system element embedded in a parallel
processing architecture" which is controlled by the
micro-engine. We assume that the Examiner has ignored the
preamble limitation of "in a parallel processing
architecture," although this is not stated. It is difficult
to tell how the "host interface logic 102" can be considered
to "control" anything since its modules 107, 108 merely
"manage communication of data between the independent
memory 103 and the host in response to writes by the host
system to the adapter interface address block 101" (col. 9,
lines 65-68).
Second, the registers pointed to by the Examiner are in
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