Appeal No. 96-3274
Application 08/173,408
the adapter interface host address space 101 and the network
interface logic does not have access to this address space.
Perhaps the Examiner meant to refer to the registers in the
adapter's memory 103 (e.g., col. 11, lines 6-10).
Third, both the host interface logic 102 and the network
interface logic 104 in figure 3 are part of the network
interface processor 14 in figure 1; the functional units of
the network interface processor are shown in figure 2. It
appears as if the Examiner has divided the network interface
processor 14, which seems to best correspond to a "network
interface module," into both a "micro-engine" and a "network
interface module." We would have liked to see some reasoning
for this interpretation.
Nevertheless, since Appellant argues only that Petersen
does not disclose a network interface module that is timed
asynchronously with respect to a micro-engine, and a
point-to-point interface, we limit our analysis to those two
differences. The Examiner admits that Petersen does not
disclose asynchronous timing or a point-to-point interface
(FR3).
Regarding the asynchronous timing limitation, the
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