Appeal No. 1996-3365
Application 08/258,357
generation circuit recited in the second half of claim 1. The
Examiner states that the combination is obvious:
because it is well known in the data
processing art that the parity generation
circuit is used in checking for errors in
groups of data bits transferred within or
between computer systems and memory
storage. (Answer-page 5.)
We agree with the Examiner that parity generation in
computer systems is well known for checking errors. However,
Appellant’s claimed implementation has not been shown by
Hillis and/or Callison. As with the Appellant, we fail to see
the structural configuration recited in claim 1.
For example, Appellant argues:
In this manner, neither Callison nor
Hillis, nor the combination thereof,
provide the structure of Claim 1 -- which
requires that the same plurality of inputs
applied to a parity generation circuit also
be inputted to a first plurality of
multiplexers via a first plurality of
busses. (Brief-page 9.)
In response, the Examiner states:
It is noted that Callison taught parity
generation circuit check 90 (see 90, fig.
5). Hillis taught a plurality of bus
multiplexers([430], fig. 5). It would have
been obvious for one of ordinary skill in
the data processing art at the time the
invention was made that the combination
5
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