Appeal No. 96-3440
Application 08/261,613
The claimed invention is an improvement over the admitted
prior art driving circuit shown in Figure 5 of the
application. The improvement is the addition of a clamping
transistor which maintains the control terminal of a pull-up
transistor at the output level of a buffer stage when the
output level is higher than the level of the power supply
voltage.
According to the examiner, the improvement was suggested
by Tarng, who shows a clamping transistor MONC in Figure 10A.
In response, appellant argues:
The purpose of the recited “clamping
transistor” is to maintain the control terminal of
the “pull-up transistor” at the output level of the
buffer stage when the output level is higher than
the level of the power supply voltage V . Although
cc
Tarng shows that a “voltage clamping circuit” per se
is generally known, the context in which the
“voltage clamping circuit” is disclosed in Tarng
significantly differs from the purpose of the
defined “clamping transistor” comprising a component
of the “driving circuit” as defined in Claims 2-10
on appeal. Thus, Tarng describes the “voltage
clamping circuit” as illustrated in Figure 7 of the
drawings thereof which includes parallel branches of
serially connected CMOS transistors MCNO and MCPO in
a first branch and MONC and MOPC in a second branch.
It is not at all apparent from the Examiner’s brief
comments as to how he proposes to incorporate the
voltage clamping circuit as disclosed in Figure 7 of
Tarng into the conventional driving circuit
illustrated in Figure 5 of the drawings of this
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