Appeal No. 96-3978
Application No. 08/092,628
application. Claims 1-20 have been canceled. An amendment
after final rejection which proposed changes to the
specification was filed June 5, 1995 and was indicated as
being entered on the filing of appeal by the Examiner in the
advisory action dated June 28, 1995.
The disclosed invention relates to a computer memory
system having a memory control unit which is coupled to a
system bus for receiving memory addresses and which is further
coupled to a plurality of memory units over a memory bus. An
access speed or timing characteristic of a selected memory
unit is communicated over the memory bus to the memory control
unit in response to a transmitted memory address.
Claim 21 is illustrative of the invention and reads as
follows:
21. A memory control unit coupled during use to a system bus
for receiving memory addresses therefrom, said memory control
unit further being coupled during use to one or more memory
units by a second bus, the second bus including a plurality of
signal lines for transmitting, during a memory access cycle, a
memory address to the one or more memory units, each of said
one or more memory units being comprised of a plurality of
semiconductor memory devices having a plurality of addressable
memory storage locations, said memory control unit further
including means, coupled to and responsive to a signal
asserted on the second bus by one of the memory units selected
by the transmitted memory address, the asserted signal
indicating an access speed of the selected memory unit, for
2
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